Projects

hardware verilog

A pipelined RISC-V processor written from scratch in Verilog.

research llm

Directional-framing stress-test for factual consistency in large language models.

ml web

Two implementations of the NanoGPT architecture in TensorflowJS, with both the Layers and Models APIs.

ml infra

A pipeline for training LLMs in the shell in a streaming fashion. Created for both research and pedagogical purposes.

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